497 search results - page 24 / 100 » A Network on Chip Architecture and Design Methodology |
ASAP
2007
IEEE
15 years 1 months ago
2007
IEEE
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
146
click to vote
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
DAC
2007
ACM
16 years 26 days ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
CODES
2000
IEEE
15 years 4 months ago
2000
IEEE
Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To b...
DAC
2006
ACM
15 years 5 months ago
2006
ACM
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...