497 search results - page 25 / 100 » A Network on Chip Architecture and Design Methodology |
DAC
2007
ACM
16 years 26 days ago
2007
ACM
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
DAC
1998
ACM
16 years 25 days ago
1998
ACM
This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the gr...
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
IEEEHPCS
2010
14 years 10 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
ASPDAC
2009
ACM
15 years 3 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...