497 search results - page 26 / 100 » A Network on Chip Architecture and Design Methodology |
DAC
2009
ACM
16 years 26 days ago
2009
ACM
Semiconductor design companies are in a continuous search for design tools that address the ever increasing chip design complexity coupled with strict time-to-market schedules and...
DAC
1998
ACM
15 years 4 months ago
1998
ACM
We present a methodology for the design and analysis of power grids in the PowerPC™ microprocessors. The methodology covers the need for power grid analysis across all stages of...
FPL
2007
Springer
15 years 6 months ago
2007
Springer
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
DAC
2004
ACM
16 years 25 days ago
2004
ACM
As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear sc...
DAC
2001
ACM
16 years 25 days ago
2001
ACM
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...