497 search results - page 37 / 100 » A Network on Chip Architecture and Design Methodology |
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristic...
122
click to vote
TPDS
2008
14 years 11 months ago
2008
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
108
click to vote
TC
2008
14 years 11 months ago
2008
Security is gaining relevance in the development of embedded devices. Toward a secure system at each level of design, this paper addresses security aspects related to Network-on-Ch...
DSN
2008
IEEE
15 years 6 months ago
2008
IEEE
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...