497 search results - page 40 / 100 » A Network on Chip Architecture and Design Methodology |
111
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NOCS
2009
IEEE
15 years 6 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
DAC
2003
ACM
16 years 25 days ago
2003
ACM
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
ICASSP
2008
IEEE
15 years 6 months ago
2008
IEEE
Recently, the conventional lifting scheme that is widely used for the construction of Wavelets and 2-channel filter banks has been extended to M-channel filter banks (M > 2)....
ICCAD
2007
IEEE
15 years 8 months ago
2007
IEEE
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
117
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CODES
2003
IEEE
15 years 5 months ago
2003
IEEE
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...