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» A Network on Chip Architecture and Design Methodology
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DSD
2009
IEEE
118views Hardware» more  DSD 2009»
15 years 6 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
MASCOTS
2007
15 years 1 months ago
PerfCenter: A Methodology and Tool for Performance Analysis of Application Hosting Centers
— We present a tool, PerfCenter, that takes as input the deployment, configuration, message flow and workload details of the hardware and software servers in an application hos...
Rukma Prabhu Verlekar, Varsha Apte, Prakhar Goyal,...
CODES
2005
IEEE
15 years 5 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
SECON
2010
IEEE
14 years 9 months ago
Coexistence-Aware Scheduling for Wireless System-on-a-Chip Devices
Abstract--Today's mobile devices support many wireless technologies to achieve ubiquitous connectivity. Economic and energy constraints, however, drive the industry to impleme...
Lei Yang, Vinod Kone, Xue Yang, York Liu, Ben Y. Z...
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 6 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...