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» A Network on Chip Architecture and Design Methodology
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GLVLSI
2009
IEEE
132views VLSI» more  GLVLSI 2009»
15 years 6 months ago
Multicast routing with dynamic packet fragmentation
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper
ICSE
2004
IEEE-ACM
15 years 12 months ago
Architecture-Based Reliability Prediction for Service-Oriented Computing
In service-oriented computing, services are dynamically built as an assembly of pre-existing, independently developed, network accessible services. Hence, predicting as much as pos...
Vincenzo Grassi
DAC
2002
ACM
16 years 24 days ago
Component-based design approach for multicore SoCs
This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitive...
Ahmed Amine Jerraya, Amer Baghdadi, Damien Lyonnar...
IPPS
2006
IEEE
15 years 5 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
DAC
2004
ACM
16 years 24 days ago
Defect tolerant probabilistic design paradigm for nanotechnologies
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the trem...
Margarida F. Jacome, Chen He, Gustavo de Veciana, ...