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» A Network on Chip Architecture and Design Methodology
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WICSA
2004
15 years 1 months ago
Compositional Generation of Software Architecture Performance QN Models
Early performance analysis based on Queueing Network Models (QNM) has been often proposed to support software designers during the software development process. These approaches a...
Antinisca Di Marco, Paola Inverardi
CODES
2006
IEEE
15 years 5 months ago
Multi-processor system design with ESPAM
For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by emb...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
DAC
2010
ACM
15 years 3 months ago
Cost-driven 3D integration with interconnect layers
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...
Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna ...
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
15 years 5 months ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman
DATE
1999
IEEE
115views Hardware» more  DATE 1999»
15 years 4 months ago
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability
We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-onChip (SOC) and automatic generation of a retargetable compiler/simulato...
Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh K...