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» A Network on Chip Architecture and Design Methodology
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DAC
1999
ACM
15 years 4 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
DAC
1991
ACM
15 years 3 months ago
REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis
REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of n...
Jerry P. Hwang
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 5 months ago
Is "Network" the next "Big Idea" in design?
As the complexity of nowadays systems continues to grow, we are moving away from creating individual components from scratch, toward methodologies that emphasize composition of re...
Radu Marculescu, Jan M. Rabaey, Alberto L. Sangiov...
FPL
2008
Springer
112views Hardware» more  FPL 2008»
15 years 1 months ago
Secure FPGA configuration architecture preventing system downgrade
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a syst...
Benoît Badrignans, Reouven Elbaz, Lionel Tor...
DAC
2002
ACM
16 years 24 days ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...