497 search results - page 48 / 100 » A Network on Chip Architecture and Design Methodology |
117
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DSN
2007
IEEE
15 years 6 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
102
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ANCS
2009
ACM
14 years 9 months ago
2009
ACM
As communication-centric computing paradigm gathers momentum due to increased wire delays and excess power dissipation with technology scaling, researchers have focused their atte...
MOBIDE
2005
ACM
15 years 5 months ago
2005
ACM
In this paper, we present an extensible approach to the adaptation of Web information delivery according to different and possibly heterogeneous contexts. The approach is based o...
117
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DAC
2003
ACM
16 years 24 days ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
VLSID
2002
IEEE
16 years 6 days ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...