Sciweavers

497 search results - page 50 / 100
» A Network on Chip Architecture and Design Methodology
Sort
View
3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
15 years 6 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...
ASPLOS
2000
ACM
15 years 4 months ago
System Architecture Directions for Networked Sensors
Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. They can be deeply embedded in the p...
Jason L. Hill, Robert Szewczyk, Alec Woo, Seth Hol...
RTAS
1997
IEEE
15 years 4 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
CASES
2008
ACM
15 years 1 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
15 years 6 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...