497 search results - page 56 / 100 » A Network on Chip Architecture and Design Methodology |
115
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HPCA
2009
IEEE
16 years 11 days ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
ICS
2009
Tsinghua U.
15 years 4 months ago
2009
Tsinghua U.
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
NOCS
2007
IEEE
15 years 6 months ago
2007
IEEE
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
111
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DAC
2008
ACM
15 years 1 months ago
2008
ACM
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
DAC
2005
ACM
16 years 24 days ago
2005
ACM
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...