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» A Network on Chip Architecture and Design Methodology
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DAC
2009
ACM
16 years 25 days ago
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power c...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
SUTC
2006
IEEE
15 years 5 months ago
Design and Implementation of Ubiquitous Smart Cameras
Design aspects and software modelling for ubiquitous real-time camera system are described in this paper. We propose system architecture using a network of inexpensive cameras and...
Chang Hong Lin, Wayne Wolf, Andrew Dixon, Xenofon ...
SENSYS
2004
ACM
15 years 5 months ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
16 years 6 days ago
Bridge Over Troubled Wrappers: Automated Interface Synthesis
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
Vijay D'Silva, S. Ramesh, Arcot Sowmya
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
15 years 6 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...