Sciweavers

497 search results - page 59 / 100
» A Network on Chip Architecture and Design Methodology
Sort
View
IPPS
2003
IEEE
15 years 5 months ago
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
16 years 6 days ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
DSN
2008
IEEE
15 years 6 months ago
A study of cognitive resilience in a JPEG compressor
Many classes of applications are inherently tolerant to errors. One such class are applications designed for a human end user, where the capabilities of the human cognitive system...
Damian Nowroth, Ilia Polian, Bernd Becker
FCCM
2005
IEEE
115views VLSI» more  FCCM 2005»
15 years 5 months ago
FIFO Communication Models in Operating Systems for Reconfigurable Computing
Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating syst...
John A. Williams, Neil W. Bergmann, X. Xie
IPPS
2005
IEEE
15 years 5 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills