497 search results - page 61 / 100 » A Network on Chip Architecture and Design Methodology |
115
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BMCBI
2010
14 years 12 months ago
2010
Background: RNA structure prediction problem is a computationally complex task, especially with pseudo-knots. The problem is well-studied in existing literature and predominantly ...
101
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VLSID
2002
IEEE
16 years 5 days ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
ASPDAC
2000
ACM
15 years 4 months ago
2000
ACM
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
HOTI
2008
IEEE
15 years 6 months ago
2008
IEEE
Much of high performance technical computing has moved from shared memory architectures to message based cluster systems. The development and wide adoption of the MPI parallel pro...
108
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GLVLSI
1998
IEEE
15 years 4 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...