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» A Network on Chip Architecture and Design Methodology
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GECCO
2006
Springer
158views Optimization» more  GECCO 2006»
15 years 3 months ago
Exploring network topology evolution through evolutionary computations
We present an evolutionary methodology that explores the evolution of network topology when a uniform growth of the network traffic is considered. The network redesign problem is ...
Sami J. Habib, Alice C. Parker
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
15 years 5 months ago
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Memory and communication architectures have a significant impact on the cost, performance, and time-to-market of complex multi-processor system-on-chip (MPSoC) designs. The memory...
Sudeep Pasricha, Nikil D. Dutt
IPPS
2002
IEEE
15 years 4 months ago
Massively Parallel Solutions for Molecular Sequence Analysis
In this paper we present new approaches to high performance protein database scanning on two novel massively parallel architectures to gain supercomputer power at low cost. The ï¬...
Bertil Schmidt, Heiko Schröder, Manfred Schim...
ISPAN
2005
IEEE
15 years 5 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
DAC
2003
ACM
16 years 23 days ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...