Sciweavers

497 search results - page 76 / 100
» A Network on Chip Architecture and Design Methodology
Sort
View
ISPASS
2009
IEEE
15 years 6 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
DAC
1999
ACM
16 years 21 days ago
Java Driven Codesign and Prototyping of Networked Embedded Systems
While the number of embedded systems in consumer electronics is growing dramatically, several trends can be observed which challenge traditional codesign practice: An increasing s...
Josef Fleischmann, Klaus Buchenrieder, Rainer Kres...
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
15 years 4 months ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...
APIN
1998
139views more  APIN 1998»
14 years 11 months ago
Evolutionary Learning of Modular Neural Networks with Genetic Programming
Evolutionary design of neural networks has shown a great potential as a powerful optimization tool. However, most evolutionary neural networks have not taken advantage of the fact ...
Sung-Bae Cho, Katsunori Shimohara
CODES
2007
IEEE
15 years 6 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...