497 search results - page 77 / 100 » A Network on Chip Architecture and Design Methodology |
112
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DFT
2005
IEEE
15 years 5 months ago
2005
IEEE
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
101
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HPCA
2009
IEEE
16 years 8 days ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
ISCA
2007
IEEE
15 years 6 months ago
2007
IEEE
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
CCR
2007
14 years 11 months ago
2007
The ns-2 simulator has limited support for simulating 802.11based wireless mesh networks. We have added the following new features at the MAC and PHY layer of ns-2: (i) cumulative...
CORR
2007
Springer
14 years 11 months ago
2007
Springer
abstract such additional information as network annotations. We introduce a network topology modeling framework that treats annotations as an extended correlation profile of a net...