497 search results - page 7 / 100 » A Network on Chip Architecture and Design Methodology |
DAC
2001
ACM
15 years 10 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, includin...
FPL
2007
Springer
15 years 3 months ago
2007
Springer
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
67
Voted
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...