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» A Network on Chip Architecture and Design Methodology
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TECS
2008
122views more  TECS 2008»
14 years 9 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
86
Voted
DAC
2005
ACM
15 years 10 months ago
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
Sorin Manolache, Petru Eles, Zebo Peng
DAC
2006
ACM
15 years 10 months ago
Timing driven power gating
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang,...
ATAL
2008
Springer
14 years 11 months ago
A domain specific modeling language for multiagent systems
Software systems are becoming more and more complex with a large number of interacting partners often distributed over a network. A common dilemma faced by software engineers in b...
Christian Hahn
WOA
2001
14 years 11 months ago
How to Support Adaptive Mobile Applications
The Mobile Agent (MA) paradigm seems to be a promising solution for the design and development of distributed value-added services. However, mobility has added complexity to the d...
Antonio Corradi, Rebecca Montanari, Gianluca Tonti...