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» A Network on Chip Architecture and Design Methodology
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SIGGRAPH
1997
ACM
15 years 1 months ago
Interactive simulation of fire in virtual building environments
This paper describes the integration of the Berkeley Architectural Walkthrough Program with the National Institute of Standards and Technology’s CFAST fire simulator. The integ...
Richard W. Bukowski, Carlo H. Séquin
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
15 years 3 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
15 years 6 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
IMC
2009
ACM
15 years 4 months ago
Practical beamforming based on RSSI measurements using off-the-shelf wireless clients
WLANs have become an important last-mile technology for providing internet access within homes and enterprises. In such indoor deployments, the wireless channel suffers from signi...
Sriram Lakshmanan, Karthikeyan Sundaresan, Sampath...
PDP
2003
IEEE
15 years 2 months ago
Automatic Optimisation of Parallel Linear Algebra Routines in Systems with Variable Load
Abstract. In this work an architecture of an automatically tuned linear algebra library proposed in previous works is extended in order to adapt it to platforms where both the CPU ...
Javier Cuenca, Domingo Giménez, José...