497 search results - page 9 / 100 » A Network on Chip Architecture and Design Methodology |
FPL
2004
Springer
15 years 5 months ago
2004
Springer
Abstract. Increasing logic resources coupled with a proliferation of integrated performance enhancing primitives in high-end FPGAs results in an increased design complexity which r...
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ITNG
2007
IEEE
15 years 5 months ago
2007
IEEE
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
CODES
1999
IEEE
15 years 4 months ago
1999
IEEE
A well-known challenge during processor design is to obtain the best possible results for a typical target application domain that is generally described as a set of benchmarks. O...
HPCA
2007
IEEE
16 years 1 days ago
2007
IEEE
