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» A New Approach for Low Power Scan Testing
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ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
15 years 6 months ago
A Novel Low-Power Scan Design Technique Using Supply Gating
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukh...
CLEF
2010
Springer
14 years 10 months ago
MapReduce for Information Retrieval Evaluation: "Let's Quickly Test This on 12 TB of Data"
We propose to use MapReduce to quickly test new retrieval approaches on a cluster of machines by sequentially scanning all documents. We present a small case study in which we use ...
Djoerd Hiemstra, Claudia Hauff
85
Voted
ATS
2004
IEEE
87views Hardware» more  ATS 2004»
15 years 1 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
15 years 1 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
70
Voted
MTV
2007
IEEE
118views Hardware» more  MTV 2007»
15 years 3 months ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee