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» A New Approach for Low Power Scan Testing
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ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
15 years 3 months ago
Two efficient methods to reduce power and testing time
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
Il-soo Lee, Tony Ambler
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
15 years 1 months ago
RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...
Hao Fang, Chenguang Tong, Xu Cheng
ISBI
2011
IEEE
14 years 1 months ago
Boosting power to detect genetic associations in imaging using multi-locus, genome-wide scans and ridge regression
Most algorithms used for imaging genetics examine statistical effects of each individual genetic variant, one at a time. We developed a new approach, based on ridge regression, to...
Omid Kohannim, Derrek P. Hibar, Jason L. Stein, Ne...
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
15 years 3 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
72
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ISQED
2010
IEEE
121views Hardware» more  ISQED 2010»
15 years 2 months ago
A novel two-dimensional scan-control scheme for test-cost reduction
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
Chia-Yi Lin, Hung-Ming Chen