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» A New Approach for Low Power Scan Testing
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126
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DAC
2006
ACM
16 years 4 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
162
Voted
ICCV
2003
IEEE
16 years 5 months ago
Learning a Locality Preserving Subspace for Visual Recognition
Previous works have demonstrated that the face recognition performance can be improved significantly in low dimensional linear subspaces. Conventionally, principal component analy...
Xiaofei He, Shuicheng Yan, Yuxiao Hu, HongJiang Zh...
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 8 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
ECCV
1996
Springer
16 years 5 months ago
Imposing Hard Constraints on Soft Snakes
An approach is presented for imposing generic hard constraints on deformable models at a low computational cost, while preserving the good convergence properties of snake-like mod...
Pascal Fua, Christian Brechbühler
CCIA
2009
Springer
15 years 5 months ago
On in-vitro and in-vivo IVUS data fusion
Abstract. The design and the validation of an automatic plaque characterization technique based on Intravascular Ultrasound (IVUS) usually requires a data ground-truth. The histolo...
Francesco Ciompi, Oriol Pujol, Oriol Rodriguez-Leo...