We introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative ...
Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelik...
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
In this paper we design an iterative rounding approach for the classic prize-collecting Steiner forest problem and more generally the prize-collecting survivable Steiner network de...
This paper is devoted to the following incremental problem. Initially, a graph and a distinguished subset of vertices, called initial group, are given. This group is connected by ...
Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect inf...