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ARVLSI
1995
IEEE
146views VLSI» more  ARVLSI 1995»
15 years 2 months ago
Array-of-arrays architecture for parallel floating point multiplication
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
H. Dhanesha, K. Falakshahi, Mark Horowitz
ASAP
2006
IEEE
145views Hardware» more  ASAP 2006»
15 years 5 months ago
2D-VLIW: An Architecture Based on the Geometry of Computation
This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of...
Ricardo Santos, Rodolfo Azevedo, Guido Araujo
EURODAC
1994
IEEE
116views VHDL» more  EURODAC 1994»
15 years 3 months ago
A performance evaluator for parameterized ASIC architectures
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
Jie Gong, Daniel D. Gajski, Alex Nicolau
EVOW
2006
Springer
15 years 3 months ago
A Connectionist Architecture for the Evolution of Rhythms
In this paper we propose the use of an interactive multi-agent system for the study of rhythm evolution. The aim of the model proposed here is to show to what extent new rhythms em...
João Magalhães Martins, Eduardo Reck...
WSC
2008
15 years 1 months ago
A plug-in-based architecture for random number generation in simulation systems
Simulations often depend heavily on random numbers, yet the impact of random number generators is recognized seldom. The generation of random numbers for simulations is not trivia...
Roland Ewald, Johannes Rossel, Jan Himmelspach, Ad...