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ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
15 years 8 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras
CCS
2003
ACM
15 years 7 months ago
On the performance, feasibility, and use of forward-secure signatures
Forward-secure signatures (FSSs) have recently received much attention from the cryptographic theory community as a potentially realistic way to mitigate many of the difficulties...
Eric Cronin, Sugih Jamin, Tal Malkin, Patrick Drew...
JUCS
2000
120views more  JUCS 2000»
15 years 1 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
PAA
2010
14 years 8 months ago
A comparative study on feature extraction for fingerprint classification and performance improvements using rank-level fusion
Abstract Fingerprint classification represents an important preprocessing step in fingerprint identification, which can be very helpful in reducing the cost of searching large fing...
Uday Rajanna, Ali Erol, George Bebis
EUROSYS
2007
ACM
15 years 10 months ago
Exploiting nonstationarity for performance prediction
Real production applications ranging from enterprise applications to large e-commerce sites share a crucial but seldom-noted characteristic: The relative frequencies of transactio...
Christopher Stewart, Terence Kelly, Alex Zhang