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» A New Era of Performance Evaluation
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VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
16 years 1 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 6 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
SIGMOD
2008
ACM
140views Database» more  SIGMOD 2008»
16 years 1 months ago
Skippy: a new snapshot indexing method for time travel in the storage manager
The storage manager of a general-purpose database system can retain consistent disk page level snapshots and run application programs "back-in-time" against long-lived p...
Ross Shaull, Liuba Shrira, Hao Xu
105
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SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
15 years 8 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
ICONIP
2010
14 years 12 months ago
A New Framework for Small Sample Size Face Recognition Based on Weighted Multiple Decision Templates
In this paper a holistic method and a local method based on decision template ensemble are investigated. In addition by combining both methods, a new hybrid method for boosting the...
Mohammad Sajjad Ghaemi, Saeed Masoudnia, Reza Ebra...