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» A New Method for Interoperability Test Generation
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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 6 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
ITSSA
2006
116views more  ITSSA 2006»
14 years 11 months ago
A Genetic Programming Approach to Automated Test Generation for Object-Oriented Software
: This article proposes a new method for creating test software for object-oriented systems using a genetic programming approach. It is believed that this approach is advantageous ...
Arjan Seesing, Hans-Gerhard Groß
DAC
2007
ACM
16 years 19 days ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
TAP
2008
Springer
93views Hardware» more  TAP 2008»
14 years 11 months ago
Pex-White Box Test Generation for .NET
Pex automatically produces a small test suite with high code coverage for a .NET program. To this end, Pex performs a systematic program analysis (using dynamic symbolic execution,...
Nikolai Tillmann, Jonathan de Halleux
115
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PKC
2001
Springer
163views Cryptology» more  PKC 2001»
15 years 4 months ago
Fast Irreducibility and Subgroup Membership Testing in XTR
Abstract. We describe a new general method to perform part of the setup stage of the XTR system introduced at Crypto 2000, namely finding the trace of a generator of the XTR group...
Arjen K. Lenstra, Eric R. Verheul