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» A New Method for Interoperability Test Generation
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108
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VTS
2000
IEEE
113views Hardware» more  VTS 2000»
15 years 6 months ago
Hidden Markov and Independence Models with Patterns for Sequential BIST
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
Laurent Bréhélin, Olivier Gascuel, G...
113
Voted
FASE
2007
Springer
15 years 8 months ago
Contract-Driven Development
Although unit tests are recognized as an important tool in software development, programmers prefer to write code, rather than unit tests. Despite the emergence of tools like JUni...
Bertrand Meyer
VTS
2008
IEEE
136views Hardware» more  VTS 2008»
15 years 8 months ago
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Te...
117
Voted
ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
15 years 7 months ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
IICAI
2003
15 years 3 months ago
The Acyclic Bayesian Net Generator
Abstract. We present the Acyclic Bayesian Net Generator, a new approach to learn the structure of a Bayesian network using genetic algorithms. Due to the encoding mechanism, acycli...
Pankaj B. Gupta, Vicki H. Allan