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» A New Pipelined Array Architecture for Signed Multiplication
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SSDBM
2006
IEEE
133views Database» more  SSDBM 2006»
15 years 3 months ago
An Extensible Infrastructure for Processing Distributed Geospatial Data Streams
Although the processing of data streams has been the focus of many research efforts in several areas, the case of remotely sensed streams in scientific contexts has received less...
Carlos Rueda, Michael Gertz, Bertram Ludäsche...
IPPS
2000
IEEE
15 years 1 months ago
Optoelectronic Multi-chip Modules Based on Imaging Fiber Bundle Structures
In this paper, we present a new packaging architecture for chip-level optical interconnections based on imaging fiber bundles. Imaging fiber bundles consist of densely packed arra...
Donald M. Chiarulli, Steven P. Levitan
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 2 months ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew
IPPS
2009
IEEE
15 years 4 months ago
Parallel reconstruction of neighbor-joining trees for large multiple sequence alignments using CUDA
Computing large multiple protein sequence alignments using progressive alignment tools such as ClustalW requires several hours on state-of-the-art workstations. ClustalW uses a th...
Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
117
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RTAS
1997
IEEE
15 years 1 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford