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112
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ATS
1998
IEEE
170views Hardware» more  ATS 1998»
15 years 1 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
ISBI
2008
IEEE
15 years 10 months ago
Controlling the error in FMRI: Hypothesis testing or set estimation?
This paper describes a new methodology and associated theoretical analysis for rapid and accurate extraction of activation regions from functional MRI data. Most fMRI data analysi...
Aarti Singh, Rebecca Willett, Robert Nowak, Zachar...
79
Voted
ASPDAC
2004
ACM
102views Hardware» more  ASPDAC 2004»
15 years 2 months ago
TranGen: a SAT-based ATPG for path-oriented transition faults
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
Kai Yang, Kwang-Ting Cheng, Li-C. Wang
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 2 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
FTCS
1993
94views more  FTCS 1993»
14 years 10 months ago
Balance Testing of Logic Circuits
We present a new test response compression method called cumulative balance testing (CBT)that extends both balance testing and accumulatorcompression testing. CBT uses an accumulat...
Krishnendu Chakrabarty, John P. Hayes