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ISMVL
2007
IEEE
104views Hardware» more  ISMVL 2007»
15 years 6 months ago
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...
Mahsan Amoui, Daniel Große, Mitchell A. Thor...
ECML
2007
Springer
15 years 6 months ago
An Improved Model Selection Heuristic for AUC
Abstract. The area under the ROC curve (AUC) has been widely used to measure ranking performance for binary classification tasks. AUC only employs the classifier’s scores to ra...
Shaomin Wu, Peter A. Flach, Cèsar Ferri Ram...
EGPGV
2004
Springer
147views Visualization» more  EGPGV 2004»
15 years 5 months ago
I/O Strategies for Parallel Rendering of Large Time-Varying Volume Data
This paper presents I/O solutions for the visualization of time-varying volume data in a parallel and distributed computing environment. Depending on the number of rendering proce...
Hongfeng Yu, Kwan-Liu Ma, Joel Welling
GECCO
2004
Springer
15 years 5 months ago
Towards a Generally Applicable Self-Adapting Hybridization of Evolutionary Algorithms
When applied to real-world problems, the powerful optimization tool of Evolutionary Algorithms frequently turns out to be too time-consuming due to elaborate fitness calculations t...
Wilfried Jakob, Christian Blume, Georg Bretthauer
DATE
2003
IEEE
116views Hardware» more  DATE 2003»
15 years 5 months ago
Statistical Timing Analysis Using Bounds
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sar...