935 search results - page 15 / 187 » A New Statistical Optimization Algorithm for Gate Sizing |
109
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ICCAD
2002
IEEE
15 years 8 months ago
2002
IEEE
Reversible, or information-lossless, circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requir...
204
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WEA
2010
Springer
15 years 6 months ago
2010
Springer
Abstract. A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit – as measured ...
118
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ITC
1993
IEEE
15 years 3 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
94
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ISPD
2003
ACM
15 years 4 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
BMCBI
2010
14 years 11 months ago
2010
Background: High throughput sequencing (HTS) platforms produce gigabases of short read (<100 bp) data per run. While these short reads are adequate for resequencing application...