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» A New Statistical Optimization Algorithm for Gate Sizing
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ISPD
2012
ACM
283views Hardware» more  ISPD 2012»
13 years 7 months ago
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-H...
STOC
1996
ACM
97views Algorithms» more  STOC 1996»
15 years 3 months ago
Deterministic Restrictions in Circuit Complexity
We study the complexity of computing Boolean functions using AND, OR and NOT gates. We show that a circuit of depth d with S gates can be made to output a constant by setting O(S1...
Shiva Chaudhuri, Jaikumar Radhakrishnan
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 6 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
COMPLIFE
2006
Springer
15 years 3 months ago
A Point-Matching Based Algorithm for 3D Surface Alignment of Drug-Sized Molecules
Abstract. Molecular shapes play an important role in molecular interactions, e.g., between a protein and a ligand. The `outer' shape of a molecule can be approximated by its s...
Daniel Baum, Hans-Christian Hege
TASE
2008
IEEE
14 years 11 months ago
New Hybrid Optimization Algorithms for Machine Scheduling Problems
Dynamic programming, branch-and-bound, and constraint programming are the standard solution principles for nding optimal solutions to machine scheduling problems. We propose a new ...
Yunpeng Pan, Leyuan Shi