935 search results - page 2 / 187 » A New Statistical Optimization Algorithm for Gate Sizing |
TCAD
2008
13 years 6 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
PATMOS
2007
Springer
14 years 11 days ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
ISPD
2012
ACM
12 years 1 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
ICCAD
2005
IEEE
14 years 3 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
ISPD
2000
ACM
13 years 10 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...