935 search results - page 8 / 187 » A New Statistical Optimization Algorithm for Gate Sizing |
ISPD
1999
ACM
15 years 1 months ago
1999
ACM
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
ISPD
1998
ACM
15 years 1 months ago
1998
ACM
We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than p...
67
Voted
DAC
2007
ACM
15 years 10 months ago
2007
ACM
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
GLVLSI
2010
IEEE
14 years 11 months ago
2010
IEEE
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...