The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
Christian Pilato, Daniele Loiacono, Fabrizio Ferra...
In the last few years, new view synthesis has emerged as an important application of 3D stereo reconstruction. While the quality of stereo has improved, it is still imperfect, and...
Samuel W. Hasinoff, Sing Bing Kang, Richard Szelis...
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topo...
In this paper, we construct a new class of deformable models using new biorthogonal wavelets, named Generalized Hermite Distributed Approximating Functional (g-HDAF) Wavelets. The...
Ioannis A. Kakadiaris, Emmanuel Papadakis, Lixin S...