45 search results - page 3 / 9 » A New System Design Methodology for Wire Pipelined SoC |
DATE
2006
IEEE
14 years 9 days ago
2006
IEEE
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...
DATE
2005
IEEE
13 years 12 months ago
2005
IEEE
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carlon...
ISCAS
2008
IEEE
14 years 20 days ago
2008
IEEE
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
ICCD
2004
IEEE
14 years 3 months ago
2004
IEEE
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
ISPD
2003
ACM
13 years 11 months ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...