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» A Non-binary Parallel Arithmetic Architecture
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ACSAC
2000
IEEE
15 years 2 months ago
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
Johann Großschädl
ICCD
2002
IEEE
138views Hardware» more  ICCD 2002»
15 years 6 months ago
The Imagine Stream Processor
The Imagine Stream Processor is a single-chip programmable media processor with 48 parallel ALUs. At 400 MHz, this translates to a peak arithmetic rate of 16 GFLOPS on single-prec...
Ujval J. Kapasi, William J. Dally, Scott Rixner, J...
SAMOS
2009
Springer
15 years 2 months ago
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems...
Yahya Jan, Lech Józwiak
FPL
2009
Springer
79views Hardware» more  FPL 2009»
15 years 2 months ago
A reconfigurable architecture for the Phylogenetic Likelihood Function
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
Nikolaos Alachiotis, Alexandros Stamatakis, Euripi...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
15 years 3 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton