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ASAP
2009
IEEE
159views Hardware» more  ASAP 2009»
15 years 4 months ago
A High-Performance Hardware Architecture for Spectral Hash Algorithm
—The Spectral Hash algorithm is one of the Round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete...
Ray C. C. Cheung, Çetin K. Koç, John...
ASIACRYPT
2001
Springer
15 years 2 months ago
A Compact Rijndael Hardware Architecture with S-Box Optimization
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all...
Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji M...
COMSWARE
2007
IEEE
15 years 4 months ago
A Parallelization of ECDSA Resistant to Simple Power Analysis Attacks
The Elliptic Curve Digital Signature Algorithm admits a natural parallelization wherein the point multiplication step can be split in two parts and executed in parallel. Further pa...
Sarang Aravamuthan, Viswanatha Rao Thumparthy
SPAA
2010
ACM
15 years 2 months ago
Towards optimizing energy costs of algorithms for shared memory architectures
Energy consumption by computer systems has emerged as an important concern. However, the energy consumed in executing an algorithm cannot be inferred from its performance alone: i...
Vijay Anand Korthikanti, Gul Agha
ICIP
2005
IEEE
15 years 11 months ago
High throughput 2D DCT/IDCT processor for video coding
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron