522 search results - page 27 / 105 » A Note on Designing Logical Circuits Using SAT |
113
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AC
2002
Springer
15 years 3 months ago
2002
Springer
Abstract. Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchro...
135
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DAC
2008
ACM
16 years 4 months ago
2008
ACM
Boolean function bi-decomposition is a fundamental operation in logic synthesis. A function f(X) is bi-decomposable under a variable partition XA, XB, XC on X if it can be written...
143
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DAC
2004
ACM
16 years 4 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
96
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ISCAS
2003
IEEE
15 years 8 months ago
2003
IEEE
Abstract - A comprehensive study of ultra high-speed currentmode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically desi...
144
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CORR
2010
Springer
15 years 21 days ago
2010
Springer
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...