522 search results - page 56 / 105 » A Note on Designing Logical Circuits Using SAT |
123
Voted
ISLPED
1995
ACM
15 years 7 months ago
1995
ACM
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
108
Voted
ITC
1997
IEEE
15 years 7 months ago
1997
IEEE
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
109
Voted
ISCAS
2007
IEEE
15 years 9 months ago
2007
IEEE
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
134
Voted
ICCAD
2007
IEEE
15 years 10 months ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
133
Voted
DSD
2010
IEEE
15 years 2 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...