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» A Note on Designing Logical Circuits Using SAT
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113
Voted
IPPS
1999
IEEE
15 years 3 months ago
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic
This paperpresents new resultson anapproach for solvingsatisfiability problems (SAT), that is, creating a logic circuit that is specialized to solve each problem instance on Field ...
Takayuki Suyama, Makoto Yokoo, Akira Nagoya
ATS
2009
IEEE
142views Hardware» more  ATS 2009»
15 years 6 months ago
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
Stephan Eggersglüß, Daniel Tille, Rolf ...
SAT
2004
Springer
106views Hardware» more  SAT 2004»
15 years 5 months ago
The Optimality of a Fast CNF Conversion and its Use with SAT
Despite the widespread use and study of Boolean satisfiability for a diverse range of problem domains, encoding of problems is usually given to general propositional logic with li...
Daniel Sheridan
100
Voted
DAC
2009
ACM
16 years 19 days ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...
IJIT
2004
15 years 1 months ago
Synthesis of Logic Circuits Using Fractional-Order Dynamic Fitness Functions
This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuit...
Cecília Reis, José António Te...