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SEUS
2005
IEEE
15 years 5 months ago
Measurement-Based Worst-Case Execution Time Analysis
In the last years the number of electronic control systems has increased significantly. In order to stay competitive more and more functionality is integrated into more and more p...
Ingomar Wenzel, Raimund Kirner, Bernhard Rieder, P...
ATS
1996
IEEE
93views Hardware» more  ATS 1996»
15 years 4 months ago
Testable Design and Testing of MCMs Based on Multifrequency Scan
In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method an...
Wang-Dauh Tseng, Kuochen Wang
VLSISP
2011
358views Database» more  VLSISP 2011»
14 years 6 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
ICIP
2010
IEEE
14 years 9 months ago
Statistical modeling of the lung nodules in low dose computed tomography scans of the chest
This work presents a novel approach in automatic detection of the lung nodules and is compared with respect to parametric nodule models in terms of sensitivity and specificity. A ...
Amal A. Farag, James Graham, Salwa Elshazly, Aly F...
CODES
2006
IEEE
15 years 6 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha