24 search results - page 4 / 5 » A Novel Clocking Strategy for Dynamic Circuits |
ASPDAC
2008
ACM
13 years 8 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
ASYNC
2003
IEEE
13 years 11 months ago
2003
IEEE
High-speed asynchronous ripple FIFOs may be easily embedded in synchronous environments and can elegantly handle the problem of forwarding data between clock domains. In cases whe...
ISCA
2003
IEEE
13 years 11 months ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
GLVLSI
2007
IEEE
14 years 18 days ago
2007
IEEE
We describe an efficient, top-down strategy for overlap removal and floorplan repair which repairs overlaps in floorplans produced by placement algorithms or rough floorplanni...
SAC
2006
ACM
14 years 6 days ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...