130 search results - page 1 / 26 » A Novel Metric for Interconnect Architecture Performance |
103
Voted
DATE
2003
IEEE
15 years 6 months ago
2003
IEEE
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
114
Voted
DAC
2001
ACM
16 years 2 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
91
Voted
ISCAS
1995
IEEE
15 years 4 months ago
1995
IEEE
We present a novel technique for datapath allocation, which incorporates interconnection area and delay estimates based on dynamic oorplanning. In this approach, datapath area is ...
95
Voted
ICCD
2004
IEEE
15 years 10 months ago
2004
IEEE
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...