39 search results - page 8 / 8 » A Novel Reconfigurable Low Power Distributed Arithmetic Arch... |
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
MOBISYS
2004
ACM
14 years 5 months ago
2004
ACM
The 802.11 IEEE Standard has enabled low cost and effective wireless LAN services (WLAN). With the sales and deployment of WLAN based networks exploding, many people believe that ...
PPOPP
2009
ACM
14 years 6 months ago
2009
ACM
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
DATE
2007
IEEE
14 years 18 days ago
2007
IEEE
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...