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ARC
2010
Springer
186views Hardware» more  ARC 2010»
15 years 25 days ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
15 years 10 months ago
A Novel Method to Improve the Test Efficiency of VLSI Tests
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...
Hailong Cui, Sharad C. Seth, Shashank K. Mehta
BMCBI
2008
110views more  BMCBI 2008»
14 years 9 months ago
Predikin and PredikinDB: a computational framework for the prediction of protein kinase peptide specificity and an associated da
Background: We have previously described an approach to predicting the substrate specificity of serine-threonine protein kinases. The method, named Predikin, identifies key conser...
Neil F. W. Saunders, Ross I. Brinkworth, Thomas Hu...
ICPP
2009
IEEE
15 years 4 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
ICRA
2007
IEEE
160views Robotics» more  ICRA 2007»
15 years 3 months ago
Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots
— For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources s...
Colin D'Souza, Byung Hwa Kim, Richard M. Voyles